From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Thu, 24 Apr 2014 21:55:13 +0000 (+0200)
Subject: drm/i915: Extract intel_prepare_shared_dpll
X-Git-Tag: omap-for-v3.16/fixes-against-rc1~44^2~38^2~69
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b14b105586dc3a8221f282220da1d47bb8a85c5b;p=pandora-kernel.git

drm/i915: Extract intel_prepare_shared_dpll

This is the last piece of code which write state to the hardware in
the ironalake ->crtc_mode_set callback.

I think we could merge this with the pll->enable hook, but otoh the
ordering requirements with the ldvs port are really tricky. Doing the
FP0/1 writes up-front before we even prepare the lvds port (in the
pre_pll_enable hook) like on i9xx seems safest.

With this ilk+ platforms are now ready for runtime PM with DPMS. Since
hsw/bdw also support runtime pm besides snb we need to first make the
haswell code save before we can touch the core code.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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