From: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Date: Mon, 1 Apr 2013 18:14:28 +0000 (+0000)
Subject: MIPS: Fix ISA level which causes secondary cache init bypassing and more
X-Git-Tag: v3.9-rc6~10^2~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=adb3789264c4e8567113a0e764ad30ce6e8737f3;p=pandora-kernel.git

MIPS: Fix ISA level which causes secondary cache init bypassing and more

The commit a96102be70 introduced set_isa() where compatible ISA info is
also set aside from the one gets passed in. It means, for example, 1004K
will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
the following inappropriate:

if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
    c->isa_level == MIPS_CPU_ISA_M32R2 ||
    c->isa_level == MIPS_CPU_ISA_M64R1 ||
    c->isa_level == MIPS_CPU_ISA_M64R2)

This patch fixes it.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

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