From: Tom Rini <trini@konsulko.com>
Date: Mon, 10 Feb 2025 16:32:03 +0000 (-0600)
Subject: Merge patch series "Enable MCU ESM reset"
X-Git-Tag: v2025.04-rc2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ac5d05f0700e719c20feb1f3d96e2a5e7d3e46bd;p=pandora-u-boot.git

Merge patch series "Enable MCU ESM reset"

Judith Mendez <jm@ti.com> says:

This patch series enables ESM reset configuration in board_init_f
for am62x and am62px devices.

This is necessary in order for error events to reset the system.

This patches are tested using watchdog to reset the system via ESM.

Link: https://lore.kernel.org/r/20250129234403.574766-1-jm@ti.com
---

ac5d05f0700e719c20feb1f3d96e2a5e7d3e46bd
diff --cc arch/arm/mach-k3/am62px/am62p5_init.c
index 7a24cf39c7b,36216aac90c..14a46fa28d2
--- a/arch/arm/mach-k3/am62px/am62p5_init.c
+++ b/arch/arm/mach-k3/am62px/am62p5_init.c
@@@ -16,9 -15,9 +16,12 @@@
  #include "../sysfw-loader.h"
  #include "../common.h"
  
 +/* TISCI DEV ID for A53 Clock */
 +#define AM62PX_DEV_A53SS0_CORE_0_DEV_ID 135
 +
+ #define CTRLMMR_MCU_RST_CTRL             0x04518170
+ #define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK 0xFFFDFFFF
+ 
  struct fwl_data cbass_main_fwls[] = {
  	{ "FSS_DAT_REG3", 7, 8 },
  };
@@@ -71,62 -70,15 +74,71 @@@ static void ctrl_mmr_unlock(void
  	mmr_unlock(PADCFG_MMR1_BASE, 1);
  }
  
 +#if CONFIG_IS_ENABLED(OF_CONTROL)
 +static int get_a53_cpu_clock_index(ofnode node)
 +{
 +	int count, i;
 +	struct ofnode_phandle_args *args;
 +	ofnode clknode;
 +
 +	clknode = ofnode_path("/bus@f0000/system-controller@44043000/clock-controller");
 +	if (!ofnode_valid(clknode))
 +		return -1;
 +
 +	count = ofnode_count_phandle_with_args(node,  "assigned-clocks", "#clock-cells", 0);
 +
 +	for (i  = 0; i < count; i++) {
 +		if (!ofnode_parse_phandle_with_args(node, "assigned-clocks",
 +						    "#clock-cells", 0, i, args)) {
 +			if (ofnode_equal(clknode, args->node) &&
 +			    args->args[0] == AM62PX_DEV_A53SS0_CORE_0_DEV_ID)
 +				return i;
 +		}
 +	}
 +
 +	return -1;
 +}
 +
 +static void fixup_a53_cpu_freq_by_speed_grade(void)
 +{
 +	int index, size;
 +	u32 *rates;
 +	ofnode node;
 +
 +	node =  ofnode_path("/a53@0");
 +	if (!ofnode_valid(node))
 +		return;
 +
 +	rates = fdt_getprop_w(ofnode_to_fdt(node), ofnode_to_offset(node),
 +			      "assigned-clock-rates", &size);
 +
 +	index = get_a53_cpu_clock_index(node);
 +
 +	if (!rates || index < 0 || index >= (size / sizeof(u32))) {
 +		printf("Wrong A53 assigned-clocks configuration\n");
 +		return;
 +	}
 +
 +	rates[index] = cpu_to_fdt32(k3_get_a53_max_frequency());
 +
 +	printf("Changed A53 CPU frequency to %dHz (%c grade) in DT\n",
 +	       k3_get_a53_max_frequency(), k3_get_speed_grade());
 +}
 +#else
 +static void fixup_a53_cpu_freq_by_speed_grade(void)
 +{
 +}
 +#endif
 +
+ static __maybe_unused void enable_mcu_esm_reset(void)
+ {
+ 	/* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z  to '0' (low active) */
+ 	u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
+ 
+ 	stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK;
+ 	writel(stat, CTRLMMR_MCU_RST_CTRL);
+ }
+ 
  void board_init_f(ulong dummy)
  {
  	struct udevice *dev;
diff --cc configs/am62px_evm_r5_defconfig
index c3adfb8697a,71e49b11650..54ea4bfb620
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@@ -86,7 -87,10 +87,9 @@@ CONFIG_TI_SCI_PROTOCOL=
  CONFIG_DM_I2C=y
  CONFIG_SYS_I2C_OMAP24XX=y
  CONFIG_DM_MAILBOX=y
 -CONFIG_K3_QOS=y
  CONFIG_K3_SEC_PROXY=y
+ CONFIG_SPL_MISC=y
+ CONFIG_ESM_K3=y
  CONFIG_MMC_HS400_SUPPORT=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_ADMA=y