From: Steve Sakoman Date: Thu, 16 Sep 2010 20:33:52 +0000 (-0700) Subject: panda: bring up to date with L24.9 changes X-Git-Tag: v1.5.0~62 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=abcc567133c8d03b11a7ea527b94a5d60c7a6cdc;p=pandora-x-loader.git panda: bring up to date with L24.9 changes --- diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c index 27f0e6e..3ae25f7 100644 --- a/board/omap4430panda/clock.c +++ b/board/omap4430panda/clock.c @@ -69,6 +69,8 @@ struct dpll_param mpu_dpll_param[7] = { #ifdef CONFIG_MPU_600 /* RUN MPU @ 600 MHz */ {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, +#elif CONFIG_MPU_1000 + {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, #else {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, #endif @@ -98,6 +100,24 @@ struct dpll_param iva_dpll_param[7] = { /* CORE parameters */ struct dpll_param core_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values - DDR@200MHz*/ + {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05}, +}; + +/* CORE parameters for L3 at 190 MHz - For ES1 only*/ +struct dpll_param core_dpll_param_l3_190[7] = { /* 12M values */ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13M values */ @@ -122,6 +142,7 @@ struct dpll_param core_dpll_param[7] = { #endif }; + /* PER parameters */ struct dpll_param per_dpll_param[7] = { /* 12M values */ @@ -137,11 +158,11 @@ struct dpll_param per_dpll_param[7] = { /* 27M values */ {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 38.4M values */ -#ifdef CONFIG_OMAP4_SDC +#if 0 + /* SDC settings */ {0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03}, -#else - {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05}, #endif + {0x14, 0x00, 0x08, 0x04, 0x0c, 0x02, 0x04, 0x05}, }; /* ABE parameters */ @@ -264,17 +285,22 @@ static void configure_per_dpll(u32 clk_index) sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m); sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n); sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1); sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1); sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1); sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1); sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6); - sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1); sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7); - sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1); + +// if(omap_revision() == OMAP4430_ES1_0) +// { + /* Do this only on ES1.0 */ + sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1); +// } /* Lock the per dpll */ sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK); @@ -375,26 +401,35 @@ static void configure_core_dpll(clk_index) sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); - /* Program USB DPLL */ - dpll_param_p = &core_dpll_param[clk_index]; - + /* Program Core DPLL */ + if(omap_revision() == OMAP4430_ES1_0) + dpll_param_p = &core_dpll_param_l3_190[clk_index]; + else + dpll_param_p = &core_dpll_param[clk_index]; + /* Disable autoidle */ sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); - sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); - sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); + + if(omap_revision() == OMAP4430_ES1_0) + { + /* Do this only on ES1.0 */ + sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); + } + /* Lock the core dpll */ sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK); @@ -423,8 +458,11 @@ void configure_core_dpll_no_lock(void) sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); - /* Program USB DPLL */ - dpll_param_p = &core_dpll_param[clk_index]; + /* Program Core DPLL */ + if(omap_revision() == OMAP4430_ES1_0) + dpll_param_p = &core_dpll_param_l3_190[clk_index]; + else + dpll_param_p = &core_dpll_param[clk_index]; /* Disable autoidle */ sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); @@ -432,17 +470,22 @@ void configure_core_dpll_no_lock(void) sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); - sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); - sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); + +// if(omap_revision() == OMAP4430_ES1_0) +// { + /* Do this only on ES1.0 */ + sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); +// } return; } @@ -458,13 +501,15 @@ void lock_core_dpll(void) void lock_core_dpll_shadow(void) { + dpll_param *dpll_param_p; /* Lock the core dpll using freq update method */ *(volatile int*)0x4A004120 = 10; //(CM_CLKMODE_DPLL_CORE) + dpll_param_p = &core_dpll_param[6]; /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1, * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1 */ - *(volatile int*)0x4A004260 = 0xF0D; + *(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11); /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */ while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 ); @@ -599,9 +644,11 @@ static void enable_all_clocks(void) wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY); /* MMC clocks */ - sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 32, 0x1000002); + sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2); + sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1); //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL, LDELAY); - sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 32, 0x1000002); + sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2); + sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1); //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL, LDELAY); sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2); wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY); @@ -690,7 +737,8 @@ static void enable_all_clocks(void) //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY); sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2); //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY); - sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x1); + /* enable the 32K, 48M optional clocks and enable the module */ + sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); return; } diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c index f2857f0..ab7c06d 100644 --- a/board/omap4430panda/omap4430panda.c +++ b/board/omap4430panda/omap4430panda.c @@ -34,8 +34,6 @@ #include #endif -#define CONFIG_OMAP4_SDC 1 - /* EMIF and DMM registers */ #define EMIF1_BASE 0x4c000000 #define EMIF2_BASE 0x4d000000 @@ -62,6 +60,7 @@ #define EMIF_L3_CONFIG 0x0054 #define EMIF_L3_CFG_VAL_1 0x0058 #define EMIF_L3_CFG_VAL_2 0x005C +#define IODFT_TLGC 0x0060 #define EMIF_PERF_CNT_1 0x0080 #define EMIF_PERF_CNT_2 0x0084 #define EMIF_PERF_CNT_CFG 0x0088 @@ -129,137 +128,25 @@ * should be programmed for new OPP. */ /* Elpida 2x2Gbit */ -#ifdef CONFIG_OMAP4_SDC -#ifndef CORE_190MHZ - /* - * EMIF_SDRAM_REF_CTRL - * refresh rate = DDR_CLK / reg_refresh_rate - * 1/3.9 uS = (333MHz) / reg_refresh_rate - */ -#define SDRAM_REF_CTRL 0x0000004A -#define SDRAM_REF_CTRL_OPP100 0x0000050E -/* - * 28:25 REG_T_RP Minimum number of m_clk cycles from - * Precharge to Activate or Refresh, minus one. - * 24:21 REG_T_RCD Minimum number of m_clk cycles from - * Activate to Read or Write, minus one. - * 20:17 REG_T_WR Minimum number of m_clk cycles from last - * Write transfer to Pre-charge, minus one. - * 16:12 REG_T_RAS Minimum number of m_clk cycles from Activate - * to Pre-charge, minus one. reg_t_ras value need - * to be bigger than or equal to reg_t_rcd value. - * 11:6 REG_T_RC Minimum number of m_clk cycles from - * Activate to Activate, minus one. - * 5:3 REG_T_RRD Minimum number of m_clk cycles from - * Activate to Activate for a different bank, minus one. - * For an 8-bank, this field must be equal to - * ((tFAW/(4*tCK))-1). - * 2:0 REG_T_WTR Minimum number of m_clk cycles from last Write - */ -#define SDRAM_TIM_1 0x04442049 -#define SDRAM_TIM_1_OPP100 0x0CA8D51A - -/* - * 30:28 REG_T_XP Minimum number of m_clk cycles from - * Powerdown exit to any command other than a - * Read command, minus one. - * 24:16 REG_T_XSNR Minimum number of m_clk cycles from Self-Refresh - * exit to any command other than a Read command, - * minusone. REG_T_XSNR and REG_T_XSRD must be - * programmed with the same value. - * 15:6 REG_T_XSRD Minimum number of m_clk cycles from Self-Refresh - * exit to a Read command, - * minus one. REG_T_XSNR and REG_T_XSRD must be - * programmed with the same value. - * 5:3 REG_T_RTP Minimum number of m_clk cycles for the last - * read command to a Pre-charge command, minus one. - */ -#define SDRAM_TIM_2 0x1002008A -#define SDRAM_TIM_2_OPP100 0x202E0B92 - -/* - * 23:21 REG_T_CKESR Minimum number of m_clk cycles for which LPDDR2 - * must remain in Self Refresh, minus one. - * 20:15 REG_ZQ_ZQCS Number of m_clk clock cycles for a ZQCS command - * minus one. - * 14:13 REG_T_TDQSCKMAX Number of m_clk that satisfies tDQSCKmax for - * LPDDR2,minus one. - * 12:4 REG_T_RFC Minimum number of m_clk cycles from Refresh or - * Load - * Mode to Refresh or Activate, minus one. - * 3:0 REG_T_RAS_MAX Maximum number of reg_refresh_rate intervals - * from Activate to Precharge command. This field - * must be equal to ((tRASmax / tREFI)-1) - * rounded down to the next lower integer. - * Value for REG_T_RAS_MAX can be calculated as - * follows: - * If tRASmax = 120 us and tREFI = 15.7 us, then - * REG_T_RAS_MAX = ((120/15.7)-1) = 6.64. - * Round down to the next lower integer. - * Therefore, the programmed value must be 6 - */ -#define SDRAM_TIM_3 0x0040802F -#define SDRAM_TIM_3_OPP100 0x008EA2BF -#define SDRAM_CONFIG_INIT 0x80800EB1 -#define SDRAM_CONFIG_FINAL 0x80801AB1 -#define DDR_PHY_CTRL_1_INIT 0x849FFFF4 -#define DDR_PHY_CTRL_1_OPP100_INIT 0x849FF404 -#define DDR_PHY_CTRL_1_FINAL 0x849FFFF8 -#define DDR_PHY_CTRL_1_OPP100_FINAL 0x849FF408 -#define DDR_PHY_CTRL_2 0x00000000 -#define READ_IDLE_CTRL 0x000501FF -#define READ_IDLE_CTRL_OPP100 0x000501FF -#define PWR_MGMT_CTRL 0x40000000 -#define PWR_MGMT_CTRL_OPP100 0x80000000 - -#else /* DDR @ 380.928 MHz */ - -#define SDRAM_REF_CTRL 0x0000004A -#define SDRAM_REF_CTRL_OPP100 0x000005CD -#define SDRAM_TIM_1 0x04442049 -#define SDRAM_TIM_1_OPP100 0x10EB065A -#define SDRAM_TIM_2 0x1002008A -#define SDRAM_TIM_2_OPP100 0x20370DD2 -#define SDRAM_TIM_3 0x0040802F -#define SDRAM_TIM_3_OPP100 0x008EA2BF -#define SDRAM_CONFIG_INIT 0x80800EB1 -#define SDRAM_CONFIG_FINAL 0x80801AB1 -#define DDR_PHY_CTRL_1_INIT 0x849FFFF4 -#define DDR_PHY_CTRL_1_OPP100_INIT 0x849FF404 -#define DDR_PHY_CTRL_1_FINAL 0x849FFFF8 -#define DDR_PHY_CTRL_1_OPP100_FINAL 0x849FF408 -#define DDR_PHY_CTRL_2 0x00000000 -#define READ_IDLE_CTRL 0x000501FF -#define READ_IDLE_CTRL_OPP100 0x000501FF -#define PWR_MGMT_CTRL 0x40000000 -#define PWR_MGMT_CTRL_OPP100 0x80000000 -#endif - -#else /* ES1.0 */ -/* TODO: ES1.0 OPP100 valuse are still not popullated - * 600 MHz/200 MHz - */ #define SDRAM_REF_CTRL 0x0000004A -#define SDRAM_REF_CTRL_OPP100 0x0000050E +#define SDRAM_REF_CTRL_OPP100 0x0000030c #define SDRAM_TIM_1 0x04442049 -#define SDRAM_TIM_1_OPP100 0x0CA8D51A +#define SDRAM_TIM_1_OPP100 0x10eb066A #define SDRAM_TIM_2 0x1002008A -#define SDRAM_TIM_2_OPP100 0x202E0B92 +#define SDRAM_TIM_2_OPP100 0x20370dd2 #define SDRAM_TIM_3 0x0040802F -#define SDRAM_TIM_3_OPP100 0x008EA2BF +#define SDRAM_TIM_3_OPP100 0x00b1c33f #define SDRAM_CONFIG_INIT 0x80800EB1 -#define SDRAM_CONFIG_FINAL 0x80801AB1 -#define DDR_PHY_CTRL_1_INIT 0x849FFFF4 -#define DDR_PHY_CTRL_1_OPP100_INIT 0x849FF404 +#define SDRAM_CONFIG_FINAL 0x98801ab1 +#define DDR_PHY_CTRL_1_INIT 0x849FFFF5 #define DDR_PHY_CTRL_1_FINAL 0x849FFFF8 -#define DDR_PHY_CTRL_1_OPP100_FINAL 0x849FF408 +#define DDR_PHY_CTRL_1_OPP100 0x849FF408 #define DDR_PHY_CTRL_2 0x00000000 -#define READ_IDLE_CTRL 0x000501FF -#define READ_IDLE_CTRL_OPP100 0x000501FF -#define PWR_MGMT_CTRL 0x80000000 -#define PWR_MGMT_CTRL_OPP100 0x00000000 - -#endif +#define READ_IDLE_CTRL 0x00050139 +#define READ_IDLE_CTRL_OPP100 0x00050139 +#define PWR_MGMT_CTRL 0x4000000f +#define PWR_MGMT_CTRL_OPP100 0x4000000f +#define ZQ_CONFIG 0x50073214 /******************************************************* @@ -272,6 +159,14 @@ static inline void delay(unsigned long loops) "bne 1b" : "=r" (loops) : "0"(loops)); } + +void big_delay(unsigned int count) +{ + int i; + for (i=0; i