From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Date: Mon, 4 Aug 2025 01:24:35 +0000 (-0700)
Subject: drivers: clk: agilex: Replace status polling with wait_for_bit_le32()
X-Git-Tag: v2025.10-rc2~3^2~26
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a44423e7e920f4196a7d50fc9ec09c12ab322f89;p=pandora-u-boot.git

drivers: clk: agilex: Replace status polling with wait_for_bit_le32()

Replace cm_wait_for_fsm() function with wait_for_bit_le32() function
which supports accurate timeout.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
---

diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index b922723d8da..242740a4b00 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -1,9 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #include <log.h>
+#include <wait_bit.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/system.h>
@@ -28,21 +30,33 @@ struct socfpga_clk_plat {
  */
 static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
 {
+	void __iomem *base = plat->regs;
+
 	CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
-	cm_wait_for_fsm();
+
+	wait_for_bit_le32(base + CLKMGR_STAT,
+			  CLKMGR_STAT_BUSY, false, 20000, false);
 }
 
 static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
 {
+	void __iomem *base = plat->regs;
+
 	CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
-	cm_wait_for_fsm();
+
+	wait_for_bit_le32(base + CLKMGR_STAT,
+			  CLKMGR_STAT_BUSY, false, 20000, false);
 }
 
 /* function to write the ctrl register which requires a poll of the busy bit */
 static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
 {
+	void __iomem *base = plat->regs;
+
 	CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
-	cm_wait_for_fsm();
+
+	wait_for_bit_le32(base + CLKMGR_STAT,
+			  CLKMGR_STAT_BUSY, false, 20000, false);
 }
 
 #define MEMBUS_MAINPLL				0
@@ -239,6 +253,7 @@ static void clk_basic_init(struct udevice *dev,
 {
 	struct socfpga_clk_plat *plat = dev_get_plat(dev);
 	u32 vcocalib;
+	uintptr_t base_addr = (uintptr_t)plat->regs;
 
 	if (!cfg)
 		return;
@@ -303,7 +318,8 @@ static void clk_basic_init(struct udevice *dev,
 	/* Membus programming for peripll */
 	membus_pll_configs(plat, MEMBUS_PERPLL);
 
-	cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+	wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT),
+			  CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false);
 
 	/* Configure ping pong counters in altera group */
 	CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);