From: Catalin Marinas <catalin.marinas@arm.com>
Date: Thu, 3 Apr 2014 16:48:54 +0000 (+0100)
Subject: arm64: Implement cache_line_size() based on CTR_EL0.CWG
X-Git-Tag: omap-for-v3.16/fixes-against-rc1~91^2~10^2~46
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a41dc0e841523efe1df7fa5ad48b5e9027a921df;p=pandora-kernel.git

arm64: Implement cache_line_size() based on CTR_EL0.CWG

The hardware provides the maximum cache line size in the system via the
CTR_EL0.CWG bits. This patch implements the cache_line_size() function
to read such information, together with a sanity check if the statically
defined L1_CACHE_BYTES is smaller than the hardware value.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
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