From: Nicolin Chen Date: Wed, 23 Jul 2014 11:23:40 +0000 (+0800) Subject: ASoC: fsl_sai: Improve enable flow in fsl_sai_trigger() X-Git-Tag: omap-for-v3.17/fixes-against-rc2~144^2~5^2~18^2 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a3fdc6749edf4dcb07df3a10bbdd9850ed5fd01a;p=pandora-kernel.git ASoC: fsl_sai: Improve enable flow in fsl_sai_trigger() The previous enable flow: 1, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO) 2, Mask IRQ of Tx/Rx to enable its interrupt. 3, Enable DMA request of Tx/Rx. As this flow would enable DMA request later than TERE, the Tx FIFO would be easily emptied into underrun while Rx FIFO would be easily stuffed into overrun due to the delayed DMA transfering. This issue happened merely occational before the patch 'ASoC: fsl_sai: Reset FIFOs after disabling TE/RE' because there were useless data remaining in the FIFO for the gap. However, it manifested after FIFO reset's implemented. After this patch, the new flow: 1, Enable DMA request of Tx/Rx. 2, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO) 3, Mask IRQ of Tx/Rx to enable its interrupt. Signed-off-by: Nicolin Chen Signed-off-by: Mark Brown --- Reading git-diff-tree failed