From: Lars-Peter Clausen Date: Thu, 10 Jul 2014 09:26:28 +0000 (+0200) Subject: spi: cadence: Make sure that clock polarity changes are applied X-Git-Tag: omap-for-v3.17/fixes-against-rc2~157^2~6^3~1 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a39e65e9cc935b84f35d080e934c3fdd9ff86654;p=pandora-kernel.git spi: cadence: Make sure that clock polarity changes are applied It seems that the cadence SPI controller does not immediately change the clock polarity setting when writing the CR register. Instead the change is delayed until the next transfer starts. This happens after the chip select line has already been asserted. As a result the first transfer after a clock polarity change will generate spurious clock transitions which typically results in the SPI slave not being able to properly understand the message. Toggling the ER register seems to cause the SPI controller to apply the clock polarity changes, so implement this as a workaround to fix the issue. Signed-off-by: Lars-Peter Clausen Signed-off-by: Mark Brown --- Reading git-diff-tree failed