From: Jesse Taube <mr.bossman075@gmail.com>
Date: Thu, 17 Mar 2022 18:33:18 +0000 (-0400)
Subject: clk: imxrt: Use dts for anatop base address
X-Git-Tag: v2022.07-rc1~26^2~12
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a2d6fbf5ff54cdeb2f75708e3551ee2df680a60c;p=pandora-u-boot.git

clk: imxrt: Use dts for anatop base address

In Linux IMX and IMXRT use the device tree to hold the anatop address.
The anatop is used in clock drivers as it controls the internal PLLs
This will move the macro from asm/arch-imxrt to the device tree.
This presumably should also be done with the other IMX boards as well.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---

diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 121665a2d22..9e1b074d2e7 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -22,6 +22,10 @@
 	u-boot,dm-spl;
 };
 
+&anatop {
+	u-boot,dm-spl;
+};
+
 &clks {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 5ba314f9953..13511ebb18e 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -67,6 +67,11 @@
 			fsl,mux_mask = <0x7>;
 		};
 
+		anatop: anatop@400d8000 {
+			compatible = "fsl,imxrt-anatop";
+			reg = <0x400d8000 0x4000>;
+		};
+
 		clks: ccm@400fc000 {
 			compatible = "fsl,imxrt1020-ccm";
 			reg = <0x400fc000 0x4000>;
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 3168c2df2cf..617cece448a 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -22,6 +22,10 @@
 	u-boot,dm-spl;
 };
 
+&anatop {
+	u-boot,dm-spl;
+};
+
 &clks {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 6560a3827f0..09f4712af68 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -59,6 +59,11 @@
 			fsl,mux_mask = <0x7>;
 		};
 
+		anatop: anatop@400d8000 {
+			compatible = "fsl,imxrt-anatop";
+			reg = <0x400d8000 0x4000>;
+		};
+
 		clks: ccm@400fc000 {
 			compatible = "fsl,imxrt1050-ccm";
 			reg = <0x400fc000 0x4000>;
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h
index d01e6ca2e02..ad739caae92 100644
--- a/arch/arm/include/asm/arch-imxrt/imx-regs.h
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -15,8 +15,6 @@
 #define GPIO4_BASE_ADDR		0x401C4000
 #define GPIO5_BASE_ADDR		0x400C0000
 
-#define ANATOP_BASE_ADDR	0x400d8000
-
 #define MXS_LCDIF_BASE		0x402b8000
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
index 3f8b4df3c5a..dc91ac5adbf 100644
--- a/drivers/clk/imx/clk-imxrt1020.c
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -36,7 +36,7 @@ static int imxrt1020_clk_probe(struct udevice *dev)
 	void *base;
 
 	/* Anatop clocks */
-	base = (void *)ANATOP_BASE_ADDR;
+	base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
 	clk_dm(IMXRT1020_CLK_PLL2_SYS,
 	       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 5cb5e3bc15a..d40635d17a4 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -34,7 +34,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
 	void *base;
 
 	/* Anatop clocks */
-	base = (void *)ANATOP_BASE_ADDR;
+	base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
 	clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
 	       imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,