From: Mengdong Lin Date: Thu, 26 Jun 2014 10:45:16 +0000 (+0800) Subject: ALSA: hda - restore BCLK M/N values when resuming HSW/BDW display controller X-Git-Tag: omap-for-v3.16/fixes-rc4~46^2 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a07187c992be945ab561b370cbb49cfd72064c3c;p=pandora-kernel.git ALSA: hda - restore BCLK M/N values when resuming HSW/BDW display controller For Intel Haswell/Broadwell display HD-A controller, the 24MHz HD-A link BCLK is converted from Core Display Clock (CDCLK): BCLK = CDCLK * M / N And there are two registers EM4 and EM5 to program M, N value respectively. The EM4/EM5 values will be lost and when the display power well is disabled. BIOS programs CDCLK selected by OEM and EM4/EM5, but BIOS has no idea about display power well on/off at runtime. So the M/N can be wrong if non-default CDCLK is used when the audio controller resumes, which results in an invalid BCLK and abnormal audio playback rate. So this patch saves and restores valid M/N values on controller suspend/resume. And 'struct hda_intel' is defined to contain standard HD-A 'struct azx' and Intel specific fields, as Takashi suggested. Signed-off-by: Mengdong Lin Cc: Signed-off-by: Takashi Iwai --- Reading git-diff-tree failed