From: Anson Huang <b20788@freescale.com>
Date: Thu, 31 Jan 2013 16:23:53 +0000 (-0500)
Subject: regulators: anatop: add set_voltage_time_sel interface
X-Git-Tag: v3.9-rc1~154^2~21^2~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9ee417c07479b9a87d0808dd3c8b4ce3925983f1;p=pandora-kernel.git

regulators: anatop: add set_voltage_time_sel interface

some of anatop's regulators(cpu, vddpu and vddsoc) have
register settings about LDO's step time, which will impact
the LDO ramp up speed, need to use set_voltage_time_sel
interface to add necessary delay everytime LDOs' voltage
is increased.

offset 0x170:
bit [24-25]: cpu
bit [26-27]: vddpu
bit [28-29]: vddsoc

field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;

Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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