From: Paul Walmsley <pwalmsley@nvidia.com>
Date: Fri, 7 Jun 2013 12:19:01 +0000 (-0600)
Subject: clk: tegra: T114: add DFLL source clocks
X-Git-Tag: omap-for-v3.11/fixes-for-merge-window~27^2~8
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9e60121fd18c22851c19ec04e8e58172cb5a7d2c;p=pandora-kernel.git

clk: tegra: T114: add DFLL source clocks

Add the input clocks needed by the DFLL IP blocks.  Initialize them to
51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.

This patch is a collaboration with Peter De Schrijver
<pdeschrijver@nvidia.com>.

Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the
requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout
issues.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Andrew Chew <achew@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
---

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