From: Arun Siluvery Date: Fri, 3 Jul 2015 13:27:31 +0000 (+0100) Subject: drm/i915: Update WaFlushCoherentL3CacheLinesAtContextSwitch X-Git-Tag: omap-for-v4.3/fixes-rc1~89^2~36^2~83 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9e00084750c0f0603ec8a6ff15e0bcf78b8202bd;p=pandora-kernel.git drm/i915: Update WaFlushCoherentL3CacheLinesAtContextSwitch In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL instruction but there is a slight complication as this is applied in WA batch where the values are only initialized once. Dave identified an issue with the current implementation where the register value is read once at the beginning and it is reused; this patch corrects this by saving the register value to memory, update register with the bit of our interest and restore it back with original value. This implementation uses MI_LOAD_REGISTER_MEM which is currently only used by command parser and was using a default length of 0. This is now updated with correct length and moved to appropriate place. Cc: Chris Wilson Cc: Dave Gordon Signed-off-by: Arun Siluvery Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- Reading git-diff-tree failed