From: Catalin Marinas <catalin.marinas@arm.com>
Date: Mon, 5 Feb 2007 13:47:40 +0000 (+0100)
Subject: [ARM] 4128/1: Architecture compliant TTBR changing sequence
X-Git-Tag: v2.6.21-rc1~75^2~6^6~11
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9d99df4b10eef130dacb5f772cd589c625b03634;p=pandora-kernel.git

[ARM] 4128/1: Architecture compliant TTBR changing sequence

On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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