From: Andi Kleen Date: Sun, 10 May 2015 19:22:44 +0000 (-0700) Subject: perf/x86/intel: Add Intel Skylake PMU support X-Git-Tag: omap-for-v4.3/fixes-merge-window~24^2~24 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9a92e16fd7b4ccd9aabcbc4d42a3fb5f9a3cf4a1;p=pandora-kernel.git perf/x86/intel: Add Intel Skylake PMU support Add perf core PMU support for future Intel Skylake CPU cores. The code is based on Haswell/Broadwell. There is a new cache event list, based on the updated Haswell event list. Skylake has removed most counter constraints on basic events, so the basic constraints table now only has a single entry (plus the fixed counters). TSX support and various other setups are all shared with Haswell. Skylake has 32 LBR entries. Add a new LBR init function to set this up. The filters are all the same as Haswell. It also has a new LBR format with a separate LBR_INFO_* MSR, but that has been already added earlier. Signed-off-by: Andi Kleen Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-7-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar --- Reading git-diff-tree failed