From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Fri, 26 Oct 2012 16:42:42 +0000 (-0700)
Subject: drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3
X-Git-Tag: v3.8-rc1~82^2~192^2~26
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9a28977181724ebbd9bdc45291cf29da55a729ee;p=pandora-kernel.git

drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3

So store into the scratch space of the HWS to make sure the invalidate
occurs.

v2: use GTT address space for store, clean up #defines (Chris)
v3: use correct #define in blt ring flush (Chris)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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