From: Shobhit Kumar <shobhit.kumar@intel.com>
Date: Fri, 15 Jun 2012 18:55:14 +0000 (-0700)
Subject: drm/i915: Enable DP panel power sequencing for ValleyView
X-Git-Tag: v3.6-rc1~83^2~42^2~12
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=98364379e1d967b8a070070797498c3708e73eb7;p=pandora-kernel.git

drm/i915: Enable DP panel power sequencing for ValleyView

VLV supports two dp panels, there are two set of panel power sequence
registers which needed to be programmed based on the configured
pipe. This patch add supports for the same

Acked-by: Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Beeresh G <beeresh.g@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Drop the lone hunk and only keep the register definitions - I
loathe incomplete bandaids. Also add a comment that this is for vlv.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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