From: Chen-Yu Tsai Date: Wed, 12 Nov 2014 18:08:31 +0000 (+0800) Subject: clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output X-Git-Tag: omap-for-v3.19/fixes-rc1~9^2~15^2~1 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=95e94c1fadcd1959857db45c2e11810a893badd0;p=pandora-kernel.git clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output Some clock modules on the A31 use PLL6x2 as one of their inputs. This patch changes the PLL6 implementation for A31 to a divs clock, i.e. clock with multiple outputs that have different dividers. The first output will be the normal PLL6 output, and the second will be PLL6x2. This patch fixes the PLL6 N factor in the clock driver, and removes any /2 dividers in the PLL6 factors clock part. The N factor counts from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Reading git-diff-tree failed