From: Alexander Sverdlin Date: Thu, 11 Jun 2015 09:35:26 +0000 (+0200) Subject: i2c: davinci: Optimize SCL generation X-Git-Tag: omap-for-v4.2/fixes-rc1^2~108^2~9 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=955fc950795d1c9f11f220f449ecb29b92985ee2;p=pandora-kernel.git i2c: davinci: Optimize SCL generation There are several cases where current clock configuration algorithm produces not optimal results: - truncation in "clk" calculation leads to the fact that actual BUS frequency will be always higher than spec except two exact module frequences 8MHz and 12MHz in the whole 7-12MHz range of permitted frequences - driver configures SCL HIGH to LOW ratio always 1 to 1 and this doesn't work well in 400kHz case, namely minimum time of LOW state (according to I2C Spec 2.1) 1.3us will not be fulfilled. HIGH to LOW ratio 1 to 2 would be more approriate here. Signed-off-by: Michael Lawnick Signed-off-by: Alexander Sverdlin Signed-off-by: Wolfram Sang --- Reading git-diff-tree failed