From: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Date: Thu, 27 Sep 2012 13:43:01 +0000 (+0530)
Subject: drm/i915: Set aux clk to 100MHz for Valleyview
X-Git-Tag: v3.8-rc1~82^2~192^2~220
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9473c8f485e1e3740d5aebf1de4838b615f9dedc;p=pandora-kernel.git

drm/i915: Set aux clk to 100MHz for Valleyview

Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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