From: Andreas Färber <afaerber@suse.de>
Date: Thu, 6 Nov 2014 17:22:10 +0000 (+0100)
Subject: ARM: dts: zynq: Enable PL clocks for Parallella
X-Git-Tag: omap-for-v3.19/fixes-for-merge-window~138^2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c;p=pandora-kernel.git

ARM: dts: zynq: Enable PL clocks for Parallella

The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.

Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.

Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.

Cc: <stable@vger.kernel.org> # 3.17.x
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
---

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