From: Marek Vasut Date: Tue, 25 Mar 2025 22:43:29 +0000 (+0100) Subject: ram: renesas: dbsc5: Clarify MR27/MR28/MR57 register operations X-Git-Tag: v2025.07-rc1~18^2~10^2~4 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8fbf39698cbe972ddbef8084c1e1cc5ff4239d63;p=pandora-u-boot.git ram: renesas: dbsc5: Clarify MR27/MR28/MR57 register operations Rename dbsc5_ddr_register_read() to dbsc5_ddr_register_mr27_mr57_read() and dbsc5_ddr_register_set() to dbsc5_ddr_register_mr28_set() to make it clear what those functions really do. No functional change. Signed-off-by: Marek Vasut --- diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c index 6f78afb0ab5..e0c4e5fe6c0 100644 --- a/drivers/ram/renesas/dbsc5/dram.c +++ b/drivers/ram/renesas/dbsc5/dram.c @@ -4085,25 +4085,25 @@ static u32 dbsc5_read_training(struct udevice *dev) } /** - * dbsc5_ddr_register_set() - DDR mode register setting + * dbsc5_ddr_register_mr28_set() - DDR mode register MR28 set * @dev: DBSC5 device * * Set the mode register 28 of the SDRAM. * ZQ Mode: Command-Based ZQ Calibration * ZQ interval: Background Cal Interval < 64ms */ -static void dbsc5_ddr_register_set(struct udevice *dev) +static void dbsc5_ddr_register_mr28_set(struct udevice *dev) { dbsc5_send_dbcmd2(dev, 0xE841C24); } /** - * dbsc5_ddr_register_read() - DDR mode register read + * dbsc5_ddr_register_mr27_mr57_read() - DDR mode register MR27/MR57 read * @dev: DBSC5 device * * Set the mode register 27 and 57 of the SDRAM. */ -static void dbsc5_ddr_register_read(struct udevice *dev) +static void dbsc5_ddr_register_mr27_mr57_read(struct udevice *dev) { struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); @@ -4278,10 +4278,10 @@ static u32 dbsc5_init_ddr(struct udevice *dev) /* setup DDR mode registers */ /* MRS */ - dbsc5_ddr_register_set(dev); + dbsc5_ddr_register_mr28_set(dev); /* MRR */ - dbsc5_ddr_register_read(dev); + dbsc5_ddr_register_mr27_mr57_read(dev); /* training complete, setup DBSC */ dbsc5_dbsc_regset_post(dev);