From: Dinh Nguyen <dinguyen@altera.com>
Date: Wed, 16 Apr 2014 20:05:15 +0000 (-0500)
Subject: ARM: socfpga: dts: Add div-reg to the main_pll clocks
X-Git-Tag: omap-for-v3.16/fixes-against-rc1~39^2~41^2~27^2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8cb289ed60668d3350dda5aa19b4fa1dce1c07f1;p=pandora-kernel.git

ARM: socfpga: dts: Add div-reg to the main_pll clocks

The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.

Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---

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