From: Ezequiel Garcia Date: Wed, 8 Apr 2015 17:03:16 +0000 (-0700) Subject: spi: img-spfi: Control CS lines with GPIO X-Git-Tag: omap-for-v4.2/o2_dc~166^2~6^2 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8c2c8c03cdcb;p=pandora-kernel.git spi: img-spfi: Control CS lines with GPIO When the CONTINUE bit is set, the interrupt status we are polling to identify if a transaction has finished can be sporadic. Even though the transfer has finished, the interrupt status may erroneously indicate that there is still data in the FIFO. This behaviour causes random timeouts in large PIO transfers. Instead of using the CONTINUE bit to control the CS lines, use the SPI core's CS GPIO handling. Also, now that the CONTINUE bit is not being used, we can poll for the ALLDONE interrupt to indicate transfer completion. Signed-off-by: Sifan Naeem Signed-off-by: Ezequiel Garcia Signed-off-by: Andrew Bresticker Signed-off-by: Mark Brown --- Reading git-diff-tree failed