From: Mihai Caraman Date: Mon, 6 Aug 2012 03:27:07 +0000 (+0000) Subject: powerpc/booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int X-Git-Tag: omap-for-v3.7-rc1/fixes-cpufreq-signed~10^2~85 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8b64a9dfb091f1eca8b7e58da82f1e7d1d5fe0ad;p=pandora-kernel.git powerpc/booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests. Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest SPRG4-7 registers will be clobbered. For bolted TLB miss exception handlers, which is the version currently supported by KVM, use SPRN_SPRG_GEN_SCRATCH aka SPRG0 instead of SPRN_SPRG_TLB_SCRATCH aka SPRG6. Keep using TLB PACA slots to fit in one 64-byte cache line. For critical exception handlers use SPRG3 instead of SPRG7. Provide a routine to store and restore user-visible SPRGs. This will be subsequently used to restore VDSO information in SPRG3. Add EX_R13 to paca slots to free up SPRG3 and change the critical exception epilog to use it. Signed-off-by: Mihai Caraman Signed-off-by: Benjamin Herrenschmidt --- Reading git-diff-tree failed