From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: Sun, 30 Mar 2025 16:24:21 +0000 (+0200)
Subject: riscv: dts: jh7110: add bootph-pre-ram for &pllclk
X-Git-Tag: v2025.07-rc1~48^2~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=8b3f2eb7d8912204bda2d914b8a9a1ce1c31bb5c;p=pandora-u-boot.git

riscv: dts: jh7110: add bootph-pre-ram for &pllclk

Since commit f98cd471f06b ("clk: clk-composite: Resolve parent clock by
name") the StarFive VisionFive 2 board fails to boot.

Before that patch the SPL debug UART showed warnings like:

    clk_register: failed to get pll0_out device (parent of perh_root)
    clk_register: failed to get pll0_out device (parent of qspi_ref_src)
    clk_register: failed to get pll0_out device (parent of usb_125m)
    clk_register: failed to get pll0_out device (parent of gmac_src)
    clk_register: failed to get pll0_out device (parent of gmac1_gtxclk)
    clk_register: failed to get pll0_out device (parent of gmac0_gtxclk)

The &pllclk clock needs to be enabled early.

Fixes: f98cd471f06b ("clk: clk-composite: Resolve parent clock by name")
Suggested-by: Marek Vasut <marex@denx.de>
Tested-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index ce7d9e16961..a9e318c4a31 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -102,6 +102,10 @@
 	bootph-pre-ram;
 };
 
+&pllclk {
+	bootph-pre-ram;
+};
+
 &syscrg {
 	bootph-pre-ram;
 };