From: Alex Deucher <alexdeucher@gmail.com>
Date: Fri, 20 May 2011 08:34:17 +0000 (-0400)
Subject: drm/radeon/kms: fix up DP clock programming on DCE4/5
X-Git-Tag: v3.0-rc3~42^2~42
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=86a94defe2b88380c28547d7053633b26a397d42;p=pandora-kernel.git

drm/radeon/kms: fix up DP clock programming on DCE4/5

In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
depending on the asic.  The crtc virtual pixel clock is derived from
the DP ref clock.

- DCE4: PPLL or ext clock
- DCE5: DCPLL or ext clock

Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
PPLL/DCPLL programming and only program the DP DTO for the
crtc virtual pixel clock.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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