From: Simon Guinot <sguinot@lacie.com>
Date: Fri, 17 Sep 2010 21:33:51 +0000 (+0200)
Subject: dmaengine: fix interrupt clearing for mv_xor
X-Git-Tag: v2.6.36-rc6~11^2~7^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=863636828f1fcd9fdc15e24d620aa53cf18b432f;p=pandora-kernel.git

dmaengine: fix interrupt clearing for mv_xor

When using simultaneously the two DMA channels on a same engine, some
transfers are never completed. For example, an endless lock can occur
while writing heavily on a RAID5 array (with async-tx offload support
enabled).

Note that this issue can also be reproduced by using the DMA test
client.

On a same engine, the interrupt cause register is shared between two
DMA channels. This patch make sure that the cause bit is only cleared
for the requested channel.

Signed-off-by: Simon Guinot <sguinot@lacie.com>
Tested-by: Luc Saillard <luc@saillard.org>
Acked-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
---

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