From: Li, Zhen-Hua <zhen-hual@hp.com>
Date: Fri, 13 Sep 2013 06:27:32 +0000 (+0800)
Subject: x86/iommu: correct ICS register offset
X-Git-Tag: v3.12-rc4~17^2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=82aeef0bf03684b377678c00c05e613f30dca39c;p=pandora-kernel.git

x86/iommu: correct ICS register offset

According to Intel Vt-D specs, the offset of Invalidation complete
status register should be 0x9C, not 0x98.

See Intel's VT-d spec, Revision 1.3, Chapter 10.4, Page 98;

Signed-off-by: Li, Zhen-Hua <zhen-hual@hp.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
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