From: Peter Ujfalusi <peter.ujfalusi@ti.com>
Date: Wed, 30 Apr 2014 11:39:37 +0000 (+0300)
Subject: CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck
X-Git-Tag: omap-for-v3.16/fixes-against-rc1~11^2~1^2~3
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=81c7e03acbcb68274be770134f8f04f270ffa859;p=pandora-kernel.git

CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck

In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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