From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Tue, 24 Sep 2013 18:26:25 +0000 (+0300)
Subject: drm/i915: Clarify VLV PLL p1 limits
X-Git-Tag: v3.13-rc1~76^2~68^2~122
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=811bbf05447b17db2fb13387da9b7d553438d5c6;p=pandora-kernel.git

drm/i915: Clarify VLV PLL p1 limits

For some reason there's a sort of off by one issue with the p1 divider.
The actual p1 limits according to
VLV2_DPLL_mphy_hsdpll_frequency_table_ww6_rev1p1.xlsm is 2-3, so we should
just say that instead of saying 1-3 and avoiding the 1 via the choice of
comparison operator.

I don't know why we're using different p1 limits for intel_limits_vlv_dac
and intel_limits_vlv_hdmi, but let's preserve that for now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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