From: David S. Miller Date: Thu, 22 Dec 2011 21:23:59 +0000 (-0800) Subject: sparc64: Fix MSIQ HV call ordering in pci_sun4v_msiq_build_irq(). X-Git-Tag: v3.2-rc7~6^2 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7cc8583372a21d98a23b703ad96cab03180b5030;p=pandora-kernel.git sparc64: Fix MSIQ HV call ordering in pci_sun4v_msiq_build_irq(). This silently was working for many years and stopped working on Niagara-T3 machines. We need to set the MSIQ to VALID before we can set it's state to IDLE. On Niagara-T3, setting the state to IDLE first was causing HV_EINVAL errors. The hypervisor documentation says, rather ambiguously, that the MSIQ must be "initialized" before one can set the state. I previously understood this to mean merely that a successful setconf() operation has been performed on the MSIQ, which we have done at this point. But it seems to also mean that it has been set VALID too. Signed-off-by: David S. Miller --- Reading git-diff-tree failed