From: Peter De Schrijver <pdeschrijver@nvidia.com>
Date: Wed, 3 Apr 2013 14:40:38 +0000 (+0300)
Subject: clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
X-Git-Tag: omap-for-v3.10/dt-fixes-for-merge-window~8^2~9^2~11
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7ba28813b41120dd67329fd04dc732ea7fef05a0;p=pandora-kernel.git

clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE

Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---

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