From: Daniel Kurtz <djkurtz@chromium.org>
Date: Fri, 30 Mar 2012 11:46:37 +0000 (+0800)
Subject: drm/i915/intel_i2c: use double-buffered writes
X-Git-Tag: v3.5-rc1~83^2~81^2~83
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7a39a9d4767e8d22d60f2c4bf5eece4f4398c274;p=pandora-kernel.git

drm/i915/intel_i2c: use double-buffered writes

The GMBUS controller GMBUS3 register is double-buffered.  Take advantage
of this  by writing two 4-byte words before the first wait for HW_RDY.
This helps keep the GMBUS controller from becoming idle during long writes.

In fact, during experiments using the GMBUS interrupts, the HW_RDY
interrupt would only trigger for transactions >4 bytes after 2 writes
to GMBUS3.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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