From: Soren Brinkmann <soren.brinkmann@xilinx.com>
Date: Mon, 17 Jun 2013 22:47:40 +0000 (-0700)
Subject: clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes
X-Git-Tag: v3.11-rc6~7^2~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=765b7d4c4cb376465f81d0dd44b50861514dbcba;p=pandora-kernel.git

clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes

Zynq's Ethernet clocks are created by the following hierarchy:
	mux0 ---> div0 ---> div1 ---> mux1 ---> gate
Rate change requests on the gate have to propagate all the way up to
div0 to properly leverage all dividers. Mux1 was missing the
CLK_SET_RATE_PARENT flag, which is required to achieve this.

This does not fix a specific regression but the clock driver was merged
for 3.11-rc1, so best to fix the known bugs before the release.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: added to changelog]
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