From: Scott Wood <scottwood@freescale.com>
Date: Mon, 25 Jun 2007 19:50:41 +0000 (-0500)
Subject: [POWERPC] 8xx: Work around CPU15 erratum.
X-Git-Tag: v2.6.24-rc1~1450^2~90
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7401685242fbcbf4b0660726372c77a88c4af17d;p=pandora-kernel.git

[POWERPC] 8xx: Work around CPU15 erratum.

The CPU15 erratum on MPC8xx chips can cause incorrect code execution
under certain circumstances, where there is a conditional or indirect
branch in the last word of a page, with a target in the last cache line
of the next page.  This patch implements one of the suggested
workarounds, by forcing a TLB miss whenever execution crosses a page
boundary.  This is done by invalidating the pages before and after the
one being loaded into the TLB in the ITLB miss handler.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

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