From: Rob Herring <rob.herring@calxeda.com>
Date: Wed, 17 Apr 2013 15:46:52 +0000 (-0500)
Subject: ARM: highbank: fix cache flush ordering for cpu hotplug
X-Git-Tag: v3.9-rc8~8^2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=73053d973dd6f56472309cffa5a5d15a62dd6f96;p=pandora-kernel.git

ARM: highbank: fix cache flush ordering for cpu hotplug

The L1 data cache flush needs to be after highbank_set_cpu_jump call which
pollutes the cache with the l2x0_lock. This causes other cores to deadlock
waiting for the l2x0_lock. Moving the flush of the entire data cache after
highbank_set_cpu_jump fixes the problem. Use flush_cache_louis instead of
flush_cache_all are that is sufficient to flush only the L1 data cache.
flush_cache_louis did not exist when highbank_cpu_die was originally
written.

With PL310 errata 769419 enabled, a wmb is inserted into idle which takes
the l2x0_lock. This makes the problem much more easily hit and causes
reset to hang.

Reported-by: Paolo Pisati <p.pisati@gmail.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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