From: Vivek Gautam <gautam.vivek@samsung.com>
Date: Fri, 21 Nov 2014 13:35:46 +0000 (+0530)
Subject: usb: dwc3: exynos: Add provision for suspend clock
X-Git-Tag: omap-for-v3.19/fixes-rc1~87^2~32^2~20
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=72d996fc7a01c2e4d581a15db7d001e2799ffb29;p=pandora-kernel.git

usb: dwc3: exynos: Add provision for suspend clock

DWC3 controller on Exynos SoC series have separate control for
suspend clock which replaces pipe3_rx_pclk as clock source to
a small part of DWC3 core that operates when SS PHY is in its
lowest power state (P3) in states SS.disabled and U3.

Suggested-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
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