From: Michel Dänzer <michel.daenzer@amd.com>
Date: Thu, 31 Jul 2014 09:43:49 +0000 (+0900)
Subject: drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
X-Git-Tag: cleanup-for-v3.18~84^2~6^2~22
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=72a9987edcedb89db988079a03c9b9c65b6ec9ac;p=pandora-kernel.git

drm/radeon: Always flush the HDP cache before submitting a CS to the GPU

This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:

* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
  is performed via MMIO

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

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