From: Alex Deucher <alexdeucher@gmail.com>
Date: Fri, 20 May 2011 16:36:12 +0000 (-0400)
Subject: drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices
X-Git-Tag: v3.0-rc1~312^2^2~13
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6f15c506e0cec601fad9fabb7ded0d1811b8002f;p=pandora-kernel.git

drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices

If the ss clock is external, the CLK_REF bit needs to be set
in the SetPixelClock parameters.  This should fix DP failures
in the channel equalization loop.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
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