From: Andre Schwarz Date: Thu, 10 Jul 2008 09:53:16 +0000 (+0200) Subject: powerpc/mpc5200: PCI write combine timer X-Git-Tag: v2.6.27-rc1~1058^2~13^2~13 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6eb9d32298290b956693fd85c815b817d39a9505;p=pandora-kernel.git powerpc/mpc5200: PCI write combine timer On MPC5200 the PCI target control register (PCITCR) @ MBAR + 0xD6C is initialized with only bit 7 (Latrule disable) set. The 8-Bit write combine timer (Bits 24..31) should be also set to a reasonable value _greater zero_ (0x08 = default) since setting it to 0x00 leads to _very poor_ performance as a PCI target since external burst won't be possible at all. Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance. Signed-off-by: Andre Schwarz Signed-off-by: Grant Likely --- Reading git-diff-tree failed