From: Catalin Marinas <catalin.marinas@arm.com>
Date: Wed, 25 Jan 2012 10:54:22 +0000 (+0100)
Subject: ARM: 7302/1: Add TLB flushing for both entries in a PMD
X-Git-Tag: v3.3-rc3~27^2~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6d3ec1ae6cdcda185bd9452b2daed5145e2493a5;p=pandora-kernel.git

ARM: 7302/1: Add TLB flushing for both entries in a PMD

Linux uses two PMD entries for a PTE with the classic page table format,
covering 2MB range. However, the __pte_free_tlb() function only adds a
single TLB flush corresponding to 1MB range covering 'addr'. On
Cortex-A15, level 1 entries can be cached by the TLB independently of
the level 2 entries and without additional flushing a PMD entry would be
left pointing at the wrong PTE. The patch limits the TLB flushing range
to two 4KB pages around the 1MB boundary within PMD.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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