From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Tue, 18 Jun 2013 09:34:35 +0000 (+0530)
Subject: drivers: net: cpsw: fix cpsw clock gating issue across suspend/resume
X-Git-Tag: v3.10~13^2~31
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6d3d76f877ca061911343d5d1650458906fdf0ea;p=pandora-kernel.git

drivers: net: cpsw: fix cpsw clock gating issue across suspend/resume

Due to some hardware integration issue, CPSW sliver modules requires a
reset across suspend/resume cycle for a successful clock gating to
CPGMAC (CPSW and Davinci MDIO) in AM335x PG1.0.
This issue is fixed in PG2.x, though to support suspend/resume on PG1.0
this reset is required.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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