From: Nicolas Pitre <nico@cam.org>
Date: Thu, 24 Apr 2008 00:04:54 +0000 (+0200)
Subject: [ARM] Feroceon: speed up flushing of the entire cache
X-Git-Tag: v2.6.27-rc1~850^2~2^8~28
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6c386e58aadb90fb5d8b5be979e02d74f8be52fe;p=pandora-kernel.git

[ARM] Feroceon: speed up flushing of the entire cache

Flushing the L1 D cache with a test/clean/invalidate loop is very
easy in software, but it is not the quickest way of doing it, as
there is a lot of overhead involved in re-scanning the cache from
the beginning every time we hit a dirty line.

This patch makes proc-feroceon.S use "clean+invalidate by set/way"
loops according to possible cache configuration of Feroceon CPUs
(either direct-mapped or 4-way set associative).

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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