From: Will Deacon <will.deacon@arm.com>
Date: Mon, 13 May 2013 11:01:12 +0000 (+0100)
Subject: ARM: mm: use inner-shareable barriers for TLB and user cache operations
X-Git-Tag: v3.12-rc1~128^2^3~1^2~5
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6abdd491698a27f7df04a32ca12cc453810e4396;p=pandora-kernel.git

ARM: mm: use inner-shareable barriers for TLB and user cache operations

System-wide barriers aren't required for situations where we only need
to make visibility and ordering guarantees in the inner-shareable domain
(i.e. we are not dealing with devices or potentially incoherent CPUs).

This patch changes the v7 TLB operations, coherent_user_range and
dcache_clean_area functions to user inner-shareable barriers. For cache
maintenance, only the store access type is required to ensure completion.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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