From: Heinrich Schuchardt Date: Fri, 21 Jul 2023 16:01:18 +0000 (+0200) Subject: riscv: define a cache line size for the generic CPU X-Git-Tag: v2023.10-rc1~9^2 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6aabe229f8440c4960b904baf3aa33f692eea9a1;p=pandora-u-boot.git riscv: define a cache line size for the generic CPU The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set. Define the cache line size for QEMU on RISC-V to be 64 bytes. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng --- diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig index 897765c3c68..2baba229923 100644 --- a/arch/riscv/cpu/generic/Kconfig +++ b/arch/riscv/cpu/generic/Kconfig @@ -6,6 +6,7 @@ config GENERIC_RISCV bool select BINMAN if SPL select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)