From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Tue, 18 Jun 2013 16:20:32 +0000 (+0100)
Subject: Watchdog: fix clearing of the watchdog interrupt
X-Git-Tag: v3.11-rc1~15^2~3
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6910ceb5cababfefffc4ddc58a085a71c0ab9f22;p=pandora-kernel.git

Watchdog: fix clearing of the watchdog interrupt

The bits in BRIDGE_CAUSE are documented as RW0C - read, write 0 to
clear.  If we read the register, mask off the watchdog bit, and
write it back, we're actually clearing every interrupt which wasn't
pending at the time we read the register - and that is racy.

Fix this to only write ~WATCHDOG_BIT to the register, which means
we write as zero only the watchdog bit.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
---

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