From: Tushar Behera <tushar.behera@linaro.org>
Date: Mon, 8 Apr 2013 06:28:12 +0000 (+0900)
Subject: clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
X-Git-Tag: omap-for-v3.10/dt-fixes-for-merge-window~45^2~3^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=688f7d8c9fef621c53c7b385ff6baf62bcb6b077;p=pandora-kernel.git

clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}

In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide)
instead of RATIO bit-field (4-bit wide) for dividing clock rate.

With current common clock setup, we are using RATIO bit-field which
is creating FIFO read errors while accessing eMMC. Changing over to
use PRE_RATIO bit-field fixes this issue.

dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020)
mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 1

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
CC: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---

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