From: Alex Deucher <alexander.deucher@amd.com>
Date: Fri, 5 Jul 2013 14:05:49 +0000 (-0400)
Subject: drm/radeon: fix surface setup on r1xx
X-Git-Tag: v3.11-rc1~65^2^2~15
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=67d5ced503db5b44cb82f378c9cb3f0e77a94e7f;p=pandora-kernel.git

drm/radeon: fix surface setup on r1xx

r1xx asics have a slightly different surface register
setup compared to newer asics.  There is no specific
enable bit for macro tiling, rather, to disable macro
tiling, you need to set the surface pitch to 0.

With this fixed, the special rn50 handling can go.

Noticed-by: Mark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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