From: Alexander Duyck <alexander.h.duyck@intel.com>
Date: Fri, 18 May 2012 06:34:02 +0000 (+0000)
Subject: ixgbe: Cleanup logic for MRQC and MTQC configuration
X-Git-Tag: v3.6-rc1~125^2~118^2~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=671c0adb5cb5f3acdc93527e54cf1e379fc980b1;p=pandora-kernel.git

ixgbe: Cleanup logic for MRQC and MTQC configuration

This change is meant to make the code much more readable for MTQC and MRQC
configuration.

The big change is that I simplified much of the logic so that we are
essentially handling just 4 cases and their variants. In the cases where
RSS is disabled we are actually just programming the RETA table with all
1s resulting in a single queue RSS. In the case of SR-IOV I am treating
that as a subset of VMDq. This all results int he following configuration
for the hardware:
         DCB
         En       Dis
VMDq En  VMDQ/DCB VMDq/RSS
     Dis DCB/RSS  RSS

Cc: John Fastabend <john.r.fastabend@intel.com>
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Stephen Ko <stephen.s.ko@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---

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